Field of the Invention
The invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the invention relates to a non-volatile memory and a manufacturing method thereof.
Description of Related Art
Since a non-volatile memory can, for instance, repeatedly perform operations such as storing, reading, and erasing data, and since stored data is not lost after the non-volatile memory is shut down, the non-volatile memory has been extensively applied in personal computers and electronic equipment.
A traditional structure of non-volatile memory has a stack-gate structure, including a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate disposed on a substrate in order. When a programming or erasing operation is performed on such a flash memory device, a suitable voltage is respectively applied to the source region, the drain region, and the control gate, such that electrons are injected into a polysilicon floating gate, or electrons are pulled out from the polysilicon floating gate.
In the operation of the non-volatile memory, a greater gate-coupling ratio (GCR) between the floating gate and the control gate generally means a lower operating voltage is needed for the operation, and the operating speed and the efficiency of the flash memory are significantly increased as a result. In particular, methods of increasing the gate coupling ratio include, for instance, increasing the overlap area between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the dielectric constant (k) of the inter-gate dielectric layer between the floating gate and the control gate.
However, as the integrated circuit is being developed into a device with smaller size by increasing the density thereof, the size of the memory cells of the non-volatile memory needs to be reduced to increase the density of the non-volatile memory. In particular, the reduction in the size of the memory cells can be achieved by, for instance, a method such as reducing the gate length of the memory cells or reducing the spacing of the bit lines. However, a reduced gate length causes reduction in the channel length below the tunneling oxide layer, and therefore abnormal punch through readily occurs between the source and the drain. As a result, the electrical performance of the memory cells is significantly affected. Moreover, when programming or erasing memory cells, electrons repeatedly pass through the tunneling oxide layer, thus causing wear to the tunneling oxide layer, and as a result, the reliability of the memory device is reduced.